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Introduction
no help | Anyone using LayoutEditor's parametric cells? by anonymous - 23 Nov 2009, 14:51 CET I am very interested in getting in contact with anyone who is willing to share some example code of parametric cells for transistors, guard rings, etc. by Juergen Thies - 23 Nov 2009, 15:24 CET Have you seen the examples/libraries shipped with the LayoutEditor: by anonymous - 25 Nov 2009, 13:59 CET Thanks, I will have a look at the openCellLibrary for better understanding about layer stetup, DRC, etc. by Juergen Thies - 25 Nov 2009, 16:51 CET Do you have design rules for a CMOS transistor which can be made public? If so, please send it to me ( ideas@LayoutEditor.net ). I will generate parameterized instance for it and add it as an example to the LayoutEditor. by anonymous - 26 Nov 2009, 9:15 CET Thanks! I emailed some design rules and models yesterday. Please let me know in case you require any further info. Looking forward to the parameterized example when available. by Juergen Thies - 26 Nov 2009, 9:52 CET Thanks, i will add some setup macros and parameterized transitor examples for the MOSIS Scalable CMOS Design Rules with the next release. I will email it to you in advance in the next days. by anonymous - 26 Nov 2009, 12:08 CET Many thanks in advance for your support in this and I am looking forward to the examples in the next days! Please log in to post! The LayoutEditor™ is a program to design and edit layouts for MEMS/IC fabrication and CMOS IC design .Designing these layouts require a high precision. In IC design a sufficient resolution and a possibility of a high scaling is required. The resolution of the LayoutEditor can be set in a wide range and is normally set to 1 nano meter. A higher resolution makes no sense due to atomar structures. With this resolution the LayoutEditor can draw elements up to 4 meters. In many IC design houses this is enough for IC/MEMS which extend usually less than 0.1 meters.
The productions of MEMS/IC is done in many layers. For each of these physical CAD layers a belonging layer had to exist in the drawing. Additional logical layers are required for describing/naming purpose. So a lot of layers are needed. By default the LayoutEditor is limited to 128 layers. But it can easily be adjusted, if more layers are required.
IC Designs often contain a plenty of repeating structures. Essential for micro fabrication of these designs is therefor a hierarchical design. This means, that the complete repeating structure only exists once in a single cell. These cell is then referred multiple times in the main drawing. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
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