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The LayoutEditor™ is a program to design and edit layouts for MEMS/IC fabrication and CMOS IC design .Designing these layouts require a high precision. In IC design a sufficient resolution and a possibility of a high scaling is required. The resolution of the LayoutEditor can be set in a wide range and is normally set to 1 nano meter. A higher resolution makes no sense due to atomar structures. With this resolution the LayoutEditor can draw elements up to 4 meters. In many IC design houses this is enough for IC/MEMS which extend usually less than 0.1 meters.
The productions of MEMS/IC is done in many layers. For each of these physical CAD layers a belonging layer had to exist in the drawing. Additional logical layers are required for describing/naming purpose. So a lot of layers are needed. By default the LayoutEditor is limited to 128 layers. But it can easily be adjusted, if more layers are required.
IC Designs often contain a plenty of repeating structures. Essential for micro fabrication of these designs is therefor a hierarchical design. This means, that the complete repeating structure only exists once in a single cell. These cell is then referred multiple times in the main drawing.
Beside the above mems packaging mentioned IC design fundaments it is important to have sophisticated functions to handle all drawing elements. The layout handler has all required functions: all basic design functions, all angle elements, boolean operations, macros, fontgenerator, design rule checker, mems tools, supported format: GDSII, DXF, OASIS, CIF. If you still missing a function, you are free to write a feature request
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Schematic Driven Layout
Creating a design from a schematic is a widespread task where layout software is used. The LayoutEditor includes a schematic capture and can also read common schematic/netlist formats. The schematic is linked with the layout. This will support the design without restricting a free custom design. A netlist can be extracted for a build-in or external layout versus schematic (lvs).
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Performance
As the LayoutEditor is available as 64-bit versions for all platforms, it can be used as well for multi Gb designs. Henceforth all significant features of the LayoutEditor are optimized to handel these huge designs. So for example multi Gb GDSII files can be loaded in less than 25s/Gb, if your hard disk gives that output. Also the painting performance was improved. With bigger designs a lack of performance is automaticly detected and scarcely visible details are omitted to increase the output performance.
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Anniversary
About 5 years ago the LayoutEditor project was started. It achieved 44 downloads within the first month. Initial users made many feature requests. A quick implementation resulted in more users with more features request, ... It grown to a very popular and full featured editor which can easily keep up with high priced tools. Last month it achieved 3285 downloads.
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Design Rule Checker
Validating the design rules is an important point in the design flow. The LayoutEditor has a integrated Design Rule Checker with many different rules checks. The errors are not only display in a list, but directly visualized within the design. As a matter of course all design rule checks work on all angle elements.
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3D View
A two dimensional designing can sometimes be quit abstract. The LayoutEditor allows a fast three dimensional visualization for your design. The graphical setup can be done in few seconds. The 3D model/3D view can be exported and used for example for a FEM-analyse.
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Macros
Macros or scripts are already standard to many programs. But the LayoutEditor has the possibility to record macro from the user interface like some office programs can do. This makes the macro creating very simple and reduced the time to learn commands. The macro are written in the most common language C and can be integrated in the menu structure. A transfer to the LayoutEditor source code is possible with minimal changes.
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 User-Info
more than
31.000
downloads per year
from about 100 countries
around the world.
download protokoll extract:
intel, stanford university, aist, asml, university berkeley, ibm, university barcelona, brother, mitsubishi, cern, amd, california institute of technology, nec, stmicroelectronics, jeol, 3M, university of tokyo, bosch, triquint, elmos, toppan printing, argonne national laboratory, sharp, kla-tencor, novosibirsk scientific center, mentor graphics, seagate, honeywell, samsung, fujitsu, infineon, messachusetts institute of technology, nxp, saifun semiconductors, harvard university, applied materials, ge, los alamos national laboratory, siemens, rf monolithics, raytheon, smith, microstaq, oxford university, sanyo, toshiba, columbia university, osaka university, synopsys, ricoh, omron, anritsu, max-planck-institut, oki, vishay, national institute of standards and technology, universite louvain, agilent, fujifilm, tokyo electron, national physical laboratory, xfab, yale university, nasa, freescale, microsoft, chalmers university, austriamicrosystems, cadence, hiroshima university, ford, tyco electronics, heidelberg instrument microtechnik, chartered, ecole polytechnique de montreal, sony, matsushita electric, texas instruments, hynix, forschungszentrum karlsruhe, nec, fraunhofer institut, lucent, swiss federal institute of technology, delft university, uni trieste, university of stellenbosch, university of western ontario, uppsala university, kyushu institute of technology, japan aerospace exploration agency, national chiao tung university, pohang university, universidade estadual de campinas, instituto politecnico nacional, nanyang technological university, reseau de l'universite de franche-comte, university of oslo, university of bucharest, gdansk university of technology |
